MIC2593

Micrel

M9999-042204

18

April 2004

Status Register Slot A (STATA)

8-Bits, Read-Only

Status Register, Slot A (STATA)

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

read-only

read-only

read-only

read/write

read/write

read/write

read/write

read/write

FAULTA

MAINA

VAUXA

VAUXAF

12MVAF

12VAF

5VAF

3VAF

Bit(s)

Function

Operation

FAULTA

FAULT Status – Slot A

1 = /FAULTA pin asserted

(/FAULTA pin is LOW)

0 = /FAULTA pin de-asserted

(/FAULTA pin is HIGH)

See Notes 1 and 2

MAINA

MAIN Enable Status – Slot A

Represents the actual state (on/off) of the

four Main Power outputs for Slot A

(+12V, –12V, +5V and +3.3V)

1 = Main Power ON

0 = Main Power OFF

VAUXA

VAUX Enable Status – Slot A

Represents the actual state (on/off) of the

Auxiliary Power output for Slot A

1 = AUX Power ON

0 = AUX Power OFF

VAUXAF

Overcurrent Fault: VAUXA supply A

1 = Fault 0 = No fault

12MVAF

Overcurrent Fault: –12V supply A

1 = Fault 0 = No fault

12VAF

Overcurrent Fault: +12V supply A

1 = Fault 0 = No fault

5VAF

Overcurrent Fault: 5V supply A

1 = Fault 0 = No fault

3VAF

Overcurrent Fault: 3.3V supply A

1 = Fault 0 = No fault

Power-Up Default Value: 0000 0000

Command_Byte Value (R/W): 0000 0100

The power-up default value is 00

overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and de-assert /INT. The

status of the /FAULTA pin is not affected by reading the Status Register or by clearing active status bits.

Notes:

1.

If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA.

If FAULTA has been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA.

If an overcurrent has occurred on both a MAIN output and the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset

FAULTA.

2.

Neither the FAULTA bit nor the /FAULTA pin is active when the MIC2593 power paths are controlled by the System Management Interface. When

using SMI power path control, AUXENA and ONA pins for that slot must be tied to GND.