MIC2593 datasheet(12/26 Pages) STMICROELECTRONICS

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MIC2593

Micrel

M9999-042204

April 2004

(decade-scale) standard capacitors.

GATE(SOURCE) = 25µ

µµµµA

GATE

dv/dt (GATE)

0.001

µF

25V/ms

0.01

µF

2.5V/ms

0.1

µF

0.25V/ms

µF

0.025V/ms

Table 1. 3.3V/5V GATE Output Slew Rate Selection

For the +12V and –12V supplies, the output slew rate is

controlled by capacitors connected to the 12VSLEWA and

12VSLEWB pins. To determine the minimum value of the

slew rate capacitor, (C

SLEW), and to ensure the device does

not enter into current limit during start-up, the following

equation is used:

min

SLEW

LIM 12V 12MV

LOAD

()

]

=×

where C

LOAD is the load capacitance connected to the +12V

and –12V outputs, I

LIM[12V/12MV] are the current limit slow-trip

thresholds and I

SLEW is the slew rate charge current found in

the “Electrical Characteristics” table. The slew rate dv/dt is

computed by:

dv dt at load

C10

SLEW

(

By appropriately selecting the value of C

SLEW, the magnitude

of the inrush current will not exceed the current limit for a

given load capacitance. Since one capacitor fixes the slew

rate for both +12V and –12V, the capacitor value should be

chosen to provide the slower slew rate of the two. Table 2

depicts the

±12V output slew rate for various values of

SLEW.

SLEW = 22µ

µµµµA

GATE

dv/dt (load)

0.001

µF

22V/ms

0.01

µF

2.2V/ms

0.1

µF

0.22V/ms

µF

0.022V/ms

Table 2.

±12V Output Slew Rate Selection

Power Down Cycle

When a slot is turned off, internal switches are connected to

each of the outputs to discharge the PCI board's bypass

capacitors to ground.

Standby Mode

Standby mode is entered when any (one or more) enabled

MAIN supply input (12V

IN, 12MVIN, 5VIN and/or 3VIN) drops

below its respective UVLO threshold. The MIC2593 supplies

two 3.3V auxiliary outputs, VAUX[A/B], satisfying PCI 2.x

specifications. These outputs are fed via the VSTBY[A/B]

input and controlled by the AUXEN[A/B] inputs or via their

SMI bus Control Registers. These outputs are independent of

the MAIN outputs: should one or more of the MAIN supply

inputs move below its UVLO thresholds, VAUX[A/B] will still

function as long as VSTBY[A/B] is present. Prior to entering

standby mode, ONA and ONB (or the MAINA and MAINB bits

in the Control Registers) inputs should be de-asserted. If this

is not done, the MIC2593 will assert /FAULT and also /INT if

interrupts are enabled, when the MIC2593 detects an under-

voltage condition on a supply input.

Circuit Breaker Functions

The MIC2593 provides an electronic circuit breaker function

that protects against excessive loads, such as short circuits,

at each supply. When the current from one or more of a slot’s

MAIN outputs exceeds the current limit threshold

(50mV/R

SENSE for 3.3V and 5V, 1.0A for +12V, and/or 0.2A

for –12V) for a duration greater than the overcurrent timer,

FLT, the circuit breaker is tripped and all MAIN supplies (all

outputs except VAUX[A/B]) are shut off. Should the load

current exceed I

THFAST (+12V and –12V), or cause a MAIN

output’s V

SENSE to exceed VTHFAST (+3.3V and +5V), the

outputs are shut off with no delay. Undervoltage conditions on

the MAIN supply inputs also trip the circuit breaker, but only

when the MAIN outputs are enabled (to signal a supply input

brown-out condition).

The VAUX[A/B] outputs have their own separate circuit

breaker functions. VAUX[A/B] do not incorporate a fast-trip

threshold, but instead regulate the output current into a fault

to avoid exceeding their operating current limit. The circuit

breaker will trip due to overcurrents on VAUX[A/B] when the

overcurrent fault timer (t

FLT) expires. This use of the

overcurrent timer prevents the circuit breaker from tripping

prematurely due to brief current transients.

Following a fault condition, the outputs can be turned on

again via the ON inputs (if the fault occurred on one of the

MAIN outputs), via the AUXEN inputs (if the fault occurred on

the AUX outputs), or by cycling both ON and AUXEN (if faults

occurred on both the MAIN and AUX outputs). A fault condi-

tion can alternatively be cleared under SMI control of the

ENABLE bits in the CNTRL[A/B] registers (See Register Bits

D[1:0]). When the circuit breaker trips, /FAULT[A/B] will be

asserted if the outputs were enabled through the Hot Plug

Interface inputs. At the same time, /INT will be asserted

(unless interrupts are masked). Note that /INT is de-asserted

by writing a Logic 1 back into the respective fault bit position(s)

in the STAT[A/B] register or the Common Status Register.

The response time (t

FLT) of the MIC2593’s primary overcur-

rent detector is set by external capacitors at the CFILTER[A/B]

pins to GND. For Slot A, CFILTER[A] is located at Pin 2; for

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