WM8216

Production Data

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PD Rev 4.0 March 2007

6

ELECTRICAL CHARACTERISTICS

Test Conditions

°C, MCLK = 60MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)

Conversion rate

60

MSPS

LOWREFS=0, Max Gain

LOWREFS=0, Min Gain

0.25

3.03

Vp-p

Vp-p

Full-scale input voltage range

(see Note 1)

LOWREFS=1, Max Gain

LOWREFS=1, Min Gain

0.15

1.82

Vp-p

Vp-p

Input signal limits (see Note 2)

AGND-0.3

AVDD+0.3

V

Input capacitance

10

pF

Input switching impedance

45

Ω

Full-scale transition error

Gain = 0dB;

PGA[7:0] = 4B(hex)

20

mV

Zero-scale transition error

Gain = 0dB;

PGA[7:0] = 4B(hex)

20

mV

Differential non-linearity

DNL

0.75

LSB

Integral non-linearity

INL

2

LSB

Channel to channel gain matching

1%

%

Output noise

Min Gain

Max Gain

0.2

2.15

LSB rms

LSB rms

References

Upper reference voltage

VRT

LOWREFS=0

LOWREFS=1

1.95

2.05

1.85

2.25

V

V

Lower reference voltage

VRB

LOWREFS=0

LOWREFS=1

0.95

1.05

1.25

1.25

V

V

Input return bias voltage

VRX

1.25

V

Diff. reference voltage (VRT-VRB)

LOWREFS=0

LOWREFS=1

0.9

1.0

0.6

1.10

V

V

Output resistance VRT, VRB, VRX

1

Ω

VRLC/Reset-Level Clamp (RLC)

RLC switching impedance

45

Ω

VRLC short-circuit current

2

mA

VRLC output resistance

2

Ω

VRLC Hi-Z leakage current

VRLC = 0 to AVDD

1

µA

RLCDAC resolution

4

bits

RLCDAC step size, RLCDAC = 0

AVDD=3.3V

0.173

V/step

RLCDAC step size, RLCDAC = 1

LOWREFS = 0

0.11

V/step

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 0

AVDD=3.3V

0.4

V

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 1

LOWREFS = 0

0.4

V

RLCDAC output voltage at

code F(hex) RLCDACRNG, = 0

AVDD=3.3V

3.0

V

RLCDAC output voltage at

code F(hex), RLCDACRNG = 1

LOWREFS = 0

2.05

V

RLCDAC

DNL

-0.5

+0.5

LSB

RLCDAC

INL

+/-0.5

LSB

Notes:

1.

Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale

input range.

2.

Input signal limits are the limits within which the full-scale input voltage signal must lie.