WM8216

Production Data

w

PD Rev 4.0 March 2007

12

On power down, where DVDD1 falls first, PORB is asserted low whenever DVDD1 drops below the

minimum threshold Vpord_off.

SYMBOL

TYP

UNIT

0.6

V

1.2

V

0.6

V

0.7

V

0.6

V

Table 1 Typical POR Operation (typical values, not tested)

DEVICE DESCRIPTION

INTRODUCTION

A block diagram of the device showing the signal path is presented on the front page of this

datasheet.

The WM8216 samples up to two inputs (OINP and EINP) simultaneously. The device then processes

the sampled video signal with respect to the video reset level or an internally/externally generated

reference level using either one or two processing channels.

Each processing channel consists of an Input Sampling block with optional Reset Level Clamping

(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and a 9-bit

Programmable Gain Amplifier (PGA).

The ADC then converts each resulting analogue signal to a 10-bit digital word. The digital output from

the ADC is presented in parallel on the 10-bit wide output bus, OP[9:0]. The ten output pins can be

set to a high impedance state using either the OEB control pin or the OPD register bit.

On-chip control registers determine the configuration of the device, including the offsets and gains

applied to each channel. These registers are programmable via a serial interface.

INPUT SAMPLING

The WM8216 can sample and process up to two inputs through one or two processing channels as

follows:

Two Channel Pixel-by-pixel: Two input channels (OINP and EINP) are simultaneously sampled for

each pixel and a separate channel processes each input. The signals are then multiplexed into the

ADC, which converts both inputs within the pixel period.

Monochrome: A single chosen input (OINP or EINP) is sampled, processed by the corresponding

channel, and converted by the ADC. The choice of input and channel can be changed via the control

interface. The unused channel is powered down when this mode is selected.

RESET LEVEL CLAMPING (RLC)

To ensure that the signal applied to the WM8216 lies within the supply voltage range (0V to AVDD)

circuit clamps the WM8216 side of this capacitor to a suitable voltage through a CMOS switch during

the CCD reset period (pixel clamping) or during the black pixels (line clamping). In order for clamping

to produce correct results the input voltage during the clamping must be a constant value.

The WM8216 allows the user to control the RLC switch in a variety of ways. Odd and Even channels

are identical, each with its own clamp switch controlled by the common CLMP signal.

The method of control chosen depends upon the characteristics of the input video. The RLCEN

register bit must be set to 1 to enable clamping, otherwise the RLC switch cannot be closed (by

default RLCEN=1).