WM8216SEFLSLASHR datasheet(18/27 Pages) WOLFSON

18 / 27 page

WM8216

Production Data

PD Rev 4.0 March 2007

The ADC BLOCK then converts the analogue signal, V3, to a 10-bit unsigned digital output, D1.

The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.

CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT

The following equations describe the processing of the video and reset level signals through

the WM8216.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the

input video.

VIN - VRESET

Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

VIN - VVRLC

Eqn. 2

If VRLCDACPD = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.

If VRLCDACPD = 0, VVRLC is the output from the internal RLC DAC.

VVRLC

(VRLCSTEP

∗ RLC DAC[3:0]) + VRLCBOT

Eqn. 3

VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

The resultant signal V1 is added to the Offset DAC output.

V1 + {255mV

∗ (DAC[7:0]-127.5) } / 127.5

Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain.

∗ (0.66 + PGA[8:0]x7.34/511)

Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 10-bit unsigned number, with input range configured by

PGAFS[1:0].

D1[9:0] = INT{ (V3 /VFS)

∗ 1023} + 511

PGAFS[1:0] = 00 or 01

Eqn. 6

D1[9:0] = INT{ (V3 /VFS)

∗ 1023}

PGAFS[1:0] = 11

Eqn. 7

D1[9:0] = INT{ (V3 /VFS)

∗ 1023} + 1023

PGAFS[1:0] = 10

Eqn. 8

where the ADC full-scale range, VFS = 2V when LOWREFS=0 and VFS = 1.2V when LOWREFS=1.

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

D2[9:0] = D1[9:0]

(INVOP = 0)

Eqn. 9

D2[9:0] = 1023 – D1[9:0]

(INVOP = 1)

Eqn. 10

WM8216SEFL/R Datasheet(PDF) 18 Page - Wolfson Microelectronics plc

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