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EMC6D103 Datasheet(PDF) 49 Page - SMSC Corporation |
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EMC6D103 Datasheet(HTML) 49 Page - SMSC Corporation |
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49 / 92 page ![]() Chapter 8 Register Set Definition for the Lock and Start columns: Yes = Register is made read-only when the related bit is set; No = Register is not made read-only when the related bit is set. Table 8.1 Register Summary Reg Addr Read /Write Reg Name Bit 7 MSb Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb Default Value Lock Start 10h R/W SMSC Test Register 7 6 5 4 3 2 1 0 00h No No 1Dh R/W Offset Register Ambient 7 6 5 4 3 2 1 0 00h Yes No 1Eh R/W Offset Register 2 7 6 5 4 3 2 1 0 00h Yes No 1Fh R/W Offset Register 1 7 6 5 4 3 2 1 0 00h Yes No 20h R +2.5V Reading 7 6 5 4 3 2 1 0 N/A No No 21h R Vccp Reading 7 6 5 4 3 2 1 0 N/A No No 22h R VCC Reading 7 6 5 4 3 2 1 0 N/A No No 23h R +5V Reading 7 6 5 4 3 2 1 0 N/A No No 24h R +12V Reading 7 6 5 4 3 2 1 0 N/A No No 25h R Remote Diode 1 Temp Reading 7 6 5 4 3 2 1 0 N/A No No 26h R Internal Temp Reading 7 6 5 4 3 2 1 0 N/A No No 27h R Remote Diode 2 Temp Reading 7 6 5 4 3 2 1 0 N/A No No 28h R Tach1 LSB 7 6 5 4 3 2 1 0 N/A No No 29h R Tach1 MSB 15 14 13 12 11 10 9 8 N/A No No 2Ah R Tach2 LSB 7 6 5 4 3 2 1 0 N/A No No 2Bh R Tach2 MSB 15 14 13 12 11 10 9 8 N/A No No 2Ch R Tach3 LSB 7 6 5 4 3 2 1 0 N/A No No 2Dh R Tach3 MSB 15 14 13 12 11 10 9 8 N/A No No 2Eh R Tach4 LSB 7 6 5 4 3 2 1 0 N/A No No 2Fh R Tach4 MSB 15 14 13 12 11 10 9 8 N/A No No 30h R/W Note 8.1 PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Yes Note 8.1 No 31h R/W Note 8.1 PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Yes Note 8.1 No 32h R/W Note 8.1 PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Yes Note 8.1 No |
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