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AM29BDS643G Datasheet(PDF) 35 Page - Advanced Micro Devices |
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AM29BDS643G Datasheet(HTML) 35 Page - Advanced Micro Devices |
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35 / 49 page  May 8, 2006 25692A2 Am29BDS643G 33 D A TA SH EE T AC CHARACTERISTICS Synchronous/Burst Read Notes: 1. Figure shows total number of clock set to five. 2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency is not present if PS is not enabled. 3. If any burst address occurs at a 64-word boundary, two additional clock cycles are inserted, and is indicated by RDY. Figure 9. Burst Mode Read (66 and 54 MHz) Parameter Description 7G (40 MHz) 7M (54 MHz) 5K (66 MHz) Unit JEDEC Standard tIACC Initial Access Time Max 95 87.5 71 ns tBACC Burst Access Time Valid Clock to Output Delay Max 20 13.5 11 ns tAVDS AVD# Setup Time to CLK Min 5 4 ns tAVDH AVD# Hold Time from CLK Min 7 6 ns tAVDO AVD# High to OE# Low Min 0 0 ns tACS Address Setup Time to CLK Min 5 4 ns tACH Address Hold Time from CLK Min 7 6 ns tBDH Data Hold Time from Next Clock Cycle Max 4 4 ns tOE Output Enable to Data, PS, or RDY Valid Max 20 13.5 11 ns tCEZ Chip Enable to High Z Max 10 10 ns tOEZ Output Enable to High Z Max 10 10 ns tCES CE# Setup Time to CLK Min 5 4 ns tRDYS RDY Setup Time to CLK Min 5 4 ns tRACC Ready access time from CLK Max 20 13.5 11 ns Da Da + 1 Da + 2 Da + n OE# A/DQ0: A/DQ15 A16: A21 Aa AVD# RDY CLK CE# tCES tACS tAVDS tAVDH tAVDO tACH tBACC tRACC tOE tOEZ tCEZ tIACC tRYDS tBDH Aa 5 cycles for initial access shown. Programmable wait state function is set to 03h. 1 cycle wait state when PS enabled 18.5 ns typ. (54 MHz) Hi-Z Hi-Z Hi-Z |
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