AM29BDS643G datasheet(12/49 Pages) AMD

12 / 49 page

Am29BDS643G

25692A2 May 8, 2006

D A TA

SH EE T

tions” and “Programmable Wait State” for further

details).

The initial word is output tIACC after the rising edge of

the first CLK cycle. Subsequent words are output tBACC

after the rising edge of each successive clock cycle,

which automatically increments the internal address

counter. Note that the device has a fixed internal

address boundary that occurs every 64 words,

starting at address 00003Eh. The transition from

the highest address 3FFFFFh to 000000h is also a

boundary crossing. During the time the device is out-

putting the 64th word (address 00003Eh, 00007Eh,

0000BEh, etc.), a two cycle latency occurs before data

appears for the next address (address 00003Fh,

00007Fh, 0000BFh, etc.). The RDY output indicates

this condition to the system by pulsing low. See Figure

19.

The device will continue to output continuous, sequen-

tial burst data, wrapping around to address 000000h

after it reaches the highest addressable memory loca-

tion, until the system asserts CE# high, RESET# low,

or AVD# low in conjunction with a new address. See

Table 1. The reset command does not terminate the

burst read operation.

If the host system crosses the bank boundary while

reading in burst mode, and the device is not program-

ming or erasing, a two-cycle latency will occur as

described above. If the host system crosses the bank

boundary while the device is programming or erasing,

the device will provide asynchronous read status infor-

mation. The clock will be ignored. After the host has

completed status reads, or the device has completed

the program or erase operation, the host can restart a

burst operation using a new address and AVD# pulse.

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

8-, 16-, and 32-Word Linear Burst with Wrap Around

The remaining three modes are of the linear wrap

around design, in which a fixed number of words are

read from consecutive addresses. In each of these

modes, the burst addresses read are determined by

the group within which the starting address falls. The

groups are sized according to the number of words

read in a single burst sequence for a given mode (see

Table 2.)

Table 2.

Burst Address Groups

As an example: if the starting address in the 8-word

mode is 39h, the address range to be read would be

38 -3 Fh , and the b u rst se qu en ce w o uld b e

39-3A-3B-3C-3D-3E-3F-38h. The burst sequence

begins with the starting address written to the device,

but wraps back to the first address in the selected

group. In a similar fashion, the 16-word and 32-word

Linear Wrap modes begin their burst sequence on the

starting address written to the device, and then wrap

back to the first address in the selected address group.

Note that in these three burst read modes the

address pointer does not cross the boundary that

occurs every 64 words; thus, no wait states are

inserted (except during the initial access).

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

Programmable Wait State

The programmable wait state feature indicates to the

device the number of additional clock cycles that must

elapse after AVD# is driven active before data will be

available. Upon power up, the device defaults to the

maximum of seven total cycles. The total number of

wait states is programmable from two to seven cycles.

The wait state command sequence requires three

cycles; after the two unlock cycles, the third cycle

address should be written according to the desired wait

state as shown in Table 8. Address bits A11-A0 should

be set to 555h, while addresses bits A16-A12 set the

wait state. For further details, see “Set Configuration

Handshaking Feature

The handshaking feature allows the host system to

simply monitor the RDY signal from the device to deter-

mine when the initial word of burst data is ready to be

read. The host system should use the wait state

command sequence to set the number of wait states

for optimal burst mode operation (02h for 40 MHz

clock, 03h for 54 and 66 MHz clock). The initial word of

burst data is indicated by the rising edge of RDY after

OE# goes low.

The handshaking feature may be verified by writing the

autoselect command sequence to the device. See

“Autoselect Command Sequence” for details.

For optimal burst mode performance on devices

without the handshaking option, the host system must

set the appropriate number of wait states in the flash

device depending on such factors as clock frequency,

presence of a boundary crossing, or an odd or even

starting address. See “Set Configuration Register

Command Sequence” section for more information.

The autoselect function allows the host system to dis-

tinguish flash devices that have handshaking from

those that do not. See the “Autoselect Command

Sequence” section for more information.

Mode

Group Size

Group Address Ranges

8-word

8 words

0-7h, 8-Fh, 10-17h, 18-1Fh...

16-word

16 words

0-Fh, 10-1Fh, 20-2Fh, 30-3Fh...

32-word

32 words

00-1Fh, 20-3Fh, 40-5Fh, 60-7Fh...

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