MBM29F040C datasheet(18/41 Pages) SPANSION

18 / 41 page

MBM29F040C-55/-70/-90

DQ2

Toggle Bit II

This Toggle Bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows:

Notes: 1. These status flags apply when outputs are read from a sector that has been erase-suspended.

2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector.

Data Protection

The MBM29F040C is designed to offer protection against accidental erasure or programming caused by spurious

system level signals that may exist during power transitions. During power up the device automatically resets

the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory

contents only occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up

and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored

until the VCC level is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Mode

DQ7

DQ6

DQ2

Program

DQ7

toggles

Erase

toggles

Erase Suspend Read

(Erase-Suspended Sector)

(Note 1)

toggles

Erase Suspend Program

DQ7 (Note 2)

toggles

1 (Note 2)

MBM29F040C Datasheet(PDF) 18 Page - SPANSION

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