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MBM29F040C Datasheet(PDF) 23 Page - SPANSION |
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MBM29F040C Datasheet(HTML) 23 Page - SPANSION |
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23 / 41 page ![]() 22 MBM29F040C-55/-70/-90 s AC CHARACTERISTICS • Read Only Operations Characteristics Note: 1. Test Conditions: Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V Parameter Symbols Description Test Setup -55 (Note1) -70 (Note2) -90 (Note2) Unit JEDEC Standard tAVAV tRC Read Cycle Time — Min. 55 70 90 ns tAVQV tACC Address to Output Delay CE = VIL OE = VIL Max. 55 70 90 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max. 55 70 90 ns tGLQV tOE Output Enable to Output Delay — Max. 30 30 35 ns tEHQZ tDF Chip Enable to Output HIGH-Z — Max. 20 20 20 ns tGHQZ tDF Output Enable to Output HIGH-Z — Max. 20 20 20 ns tAXQX tOH Output Hold Time From Addresses, CE or OE, Whichever Occurs First —Min. 0 0 0 ns Figure 4 Test Conditions CL 5.0 V Diodes = IN3064 or Equivalent 2.7 k Ω Device Under Test IN3064 or Equivalent 6.2 k Ω Note: 1.CL = 30 pF including jig capacitance 2.CL = 100 pF including jig capacitance Note: 2. Test Conditions: Oput Load: 1 TTL gate and 100 pF Input rise and fall times: 5 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level Input: 0.8 and 2.0 V Output: 0.8 and 2.0 V |
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