LTM4686 datasheet(69/132 Pages) AD

69 / 132 page

LTM4683

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

A graphical representation of the aforementioned thermal

resistances is shown in Figure 34; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal oper-

ating conditions of a µModule regulator. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through the

bottom of the µModule package—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4683, be aware that there are multiple

power devices and components dissipating power, with

the consequence that the thermal resistances relative to

different junctions of components or die are not exactly

linear to total package power loss. To reconcile this com-

plication without sacrificing modeling simplicity—but

also, not ignoring practical realities—an approach has

been taken using FEA software modeling along with lab-

oratory testing in a controlled-environment chamber to

reasonably define and correlate the thermal resistance

values supplied in this data sheet: (1) Initially, FEA soft-

ware is used to accurately build the mechanical geometry

of the LTM4683 and the specified PCB with all of the cor-

rect material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

defined JEDEC environment consistent with JESD51-9

and JESD51-12 to predict power loss heat flow and

temperature readings at different interfaces that enable

the calculation of the JEDEC-defined thermal resistance

values; (3) the model and FEA software is used to evaluate

the LTM4683 with heat sink and airflow; (4) having solved

for and analyzed these thermal resistance values and sim-

ulated various operating conditions in the software model,

a thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled envi-

ronment chamber while operating the device at the same

power loss, which was simulated. The outcome of this

process and due diligence yields the set of derating curves

provided in later sections of this data sheet, along with

well-correlated JESD51-12-defined θ values provided in

the Pin Configuration section of this data sheet.

The 5V, 8V, and 12V power loss curves in Figure 35,

Figure 36, and Figure 37, respectively, can be used in

coordination with the load current derating curves in

Figure 41 through Figure 46 for calculating an approxi-

mate θJA thermal resistance for the LTM4683 with various

airflow conditions and without heat sinks. These thermal

resistances represent demonstrated performance of the

LTM4683 on hardware, a 8-layer FR4 PCB measuring

215mm × 160mm × 1.6mm using 2oz copper on all layers.

The power loss curves are taken at room temperature, and

are increased with multiplicative factors of 1.35 when the

junction temperature reaches 125°C. The derating curves

are plotted with the LTM4683’s paralleled outputs initially

sourcing up to 120A and the ambient temperature at 25°C.

The output voltages are 0.4V, 0.6V and 0.7V. These are

chosen to include the lower and higher output voltage

ranges for correlating the thermal resistance. Thermal

models are derived from several temperature measure-

ments in a controlled temperature chamber, along with

thermal modeling analysis. The junction temperatures are

monitored while the ambient temperature is increased

with and without airflow.

The power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at 125°C maximum while lowering output cur-

rent or power while increasing ambient temperature. The

decreased output current decreases the internal module

loss as the ambient temperature is increased. The moni-

tored junction temperature of 125°C minus the ambient

operating temperature specifies how much module tem-

perature rise can be allowed. As an example in Figure 43,

the load current is derated to ~84A at ~76°C ambient with

no air or heat sink, and the room temperature (25°C)

power loss for this 12VIN to 0.6VOUT at 84AOUT condition

is ~9.3W. A 12.56W loss is calculated by multiplying the

~9.3W room temperature loss from the 12VIN to 0.6VOUT

LTM4686 Datasheet(PDF) 69 Page - Analog Devices

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