| Electronic Components Datasheet Search |
|
P83CL882T/001 Datasheet(PDF) 49 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P83CL882T/001 Datasheet(HTML) 49 Page - NXP Semiconductors |
|
49 / 88 page ![]() 2001 Jun 19 49 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 6.8.3 ADDRESS REGISTER (S1ADR) The CPU can read from and write to this 8-bit SFR. S1ADR is not affected by the SIO1 hardware. The contents of this register are irrelevant when SIO1 is in a Master mode. In the Slave modes, the seven most significant bits must be loaded with the microcontrollers own slave address, and, if the least significant bit is set, the general call address (00H) is recognized; otherwise it is ignored. Reset initializes S1ADR to 00H. Table 62 Address Register (SFR address DBH) Table 63 Description of S1ADR bits 6.8.4 SERIAL STATUS REGISTER (S1STA) S1STA is an 8-bit read-only Special Function Register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possible status codes. When S1STA contains F8H, no relevant state information is available and no serial interrupt is requested. Reset initializes S1STA to F8H. All other S1STA values correspond to defined SIO1 states. When each of these states is entered, a serial interrupt is requested (SI = 1). The status codes for all possible modes of the I2C-bus interface are given in Table 66. The contents of this register may be used as a vector to a service routine. This optimizes the response time of the software and consequently that of the I2C-bus. S1STA is a read-only register. Table 64 Serial Status Register (SFR address D9H) Table 65 Description of S1STA bits 76543210 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GC BIT SYMBOL DESCRIPTION 7 to 1 SLA[6:0] These bits correspond to the 7-bit slave address which will be recognized on the incoming data stream from the I2C-bus; when the slave address is detected and the interface is enabled, a serial interrupt will be generated to the CPU. 0 GC This bit is used to determine whether the general CALL address is recognized. When a logic 0, the general CALL address is not recognized; when a logic 1, the general CALL address is recognized. 76543210 SC4 SC3 SC2 SC1 SC0 0 0 0 BIT SYMBOL DESCRIPTION 3 to 7 SC[4:0] 5-bit status code 0to2 − these three bits are held LOW |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |