P83CL882TSLASH001 datasheet(35/88 Pages) PHILIPS

35 / 88 page

2001 Jun 19

Philips Semiconductors

Product speciﬁcation

80C51 Ultra Low Power (ULP) telephony controller

P83CL882

6.5.3

TIMER/COUNTER 0 AND 1CONTROL REGISTER (TCON)

Table 38 Timer/Counter 0 and 1 Control Register (SFR address 88H)

Table 39 Description of TCON bits

Note

1. If the Timer 0 or Timer 1 is not enabled (TR0 or TR1), the clock to Timer 0/1 is switched off for power saving.

6.5.4

TIMER/COUNTER 0 AND 1MODE CONTROL REGISTER (TMOD)

Table 40 Timer/Counter 0 and 1 Mode Control Register (SFR address 89H)

Table 41 Description of TMOD bits

76543210

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

BIT

SYMBOL

DESCRIPTION

TF1

Timer 1 overﬂow ﬂag. Set by hardware on timer/counter overflow; cleared by hardware

when processor vectors to interrupt routine, or clearing the bit in software.

TR1

Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off; note 1.

TF0

Timer 0 overﬂow ﬂag. Set by hardware on timer/counter overflow; cleared by hardware

when processor vectors to interrupt routine, or by clearing the bit in software.

TR0

Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off; note 1.

IE1

Interrupt 1 edge ﬂag. Set by hardware when external interrupt edge detected; cleared

when interrupt processed.

IT1

Interrupt 1 type control bit. Set/cleared by software. If IT1 = 1, then external interrupt

is LOW-level triggered. If IT1 = 0, then external interrupt is falling edge triggered.

IE0

Interrupt 0 edge ﬂag. Set by hardware when external interrupt edge detected; cleared

when interrupt processed.

IT0

Interrupt 0 type control bit. Set/cleared by software. If IT0 = 1, then external interrupt

is LOW-level triggered. If IT0 = 0, then external interrupt is falling edge triggered.

76543210

GATE

C/TM1

GATE

C/TM1

BIT

SYMBOL

DESCRIPTION

7GATE

Gating control. When set Timer/Counter 1 is enabled only while INT1 pin is HIGH and

TR1 control pin is set; when cleared Timer 1 is enabled whenever TR1 control bit is set.

6C/T

Timer or counter selector. Cleared for timer operation (counts on fPSC); set for counter

operation (input from T1 input pin).

5M1

Timer 1 mode select. See Table 42.

4M0

3GATE

Gating control. When set Timer/Counter 0 is enabled only while INT0 pin is HIGH and

TR0 control pin is set; when cleared Timer 0 is enabled whenever TR0 control bit is set.

2C/T

Timer or counter selector. Cleared for timer operation (counts on fPSC); set for counter

operation (input from T0 input pin).

1M1

Timer 0 mode select. See Table 42.

0M0

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