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CD4440CS Datasheet(PDF) 10 Page - NXP Semiconductors |
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CD4440CS Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 20 page ![]() 1996 Dec 20 10 Philips Semiconductors Product specification Analog voice scrambler/descrambler PCD4440T 8.3 System configuration (see Fig.8) A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls message transfer is the ‘master’ and the devices that are controlled by the master are the ‘slaves’. 8.4 Acknowledge (see Fig.9) The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge after the reception of each byte. Also a master must generate an acknowledge after reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge-related clock pulse. Set-up and hold times must be taken into account to ensure that the SDA line is stable LOW during the whole high period of the acknowledge-related clock pulse. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate the stop condition. Fig.8 System configuration. MBA605 MASTER TRANSMITTER / RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER / RECEIVER SDA SCL Fig.9 Acknowledgment on the I2C-bus. MBC602 S START CONDITION 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER |
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