CD4440CS datasheet(11/20 Pages) PHILIPS

11 / 20 page

1996 Dec 20

Philips Semiconductors

Product speciﬁcation

Analog voice scrambler/descrambler

PCD4440T

8.5

Timing speciﬁcations

The PCD4440T accepts data input from a microcontroller and operates as a ‘slave receiver’ via the I2C-bus. It supports

the ‘standard’ mode of the I2C-bus, but not the ‘fast’ mode detailed in

“The I2C-bus and how to use it” document order

no. 9398 393 40011. The timing requirement are as follows:

Masters generate a bus clock with a maximum frequency of 100 kHz. Detailed timing is shown in Fig. 10, where the two

signal levels are LOW = VIL and HIGH = VIH, see Chapter 12. The time symbols are explained in Table 2. Figure 11

shows a complete data transfer.

Fig.10 Standard mode timing.

handbook, full pagewidth

MBC764

t BUF

t f

t HIGH

t SU;DAT

t SU;STO

t HD;DAT

t SU;STA

t r

t LOW

t HD;STA

SDA

SCL

SDA

Fig.11 Complete data transfer in standard mode.

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MBC765

1 - 7

STOP

ACK

ADDRESS

R/W

START

CONDITION

ACK

DATA

START

CONDITION

ACK

ADDRESS

R/W

SCL

SDA

Clock LOW minimum = 4.7

µs; clock HIGH minimum = 4 µs.

The dashed line is the acknowledgment of the receiver.

Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).

Maximum number of bytes is unrestricted.

Premature termination of transfer is allowed by generation of STOP condition.

Acknowledge clock bit must be provided by master.

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