CD4440CS datasheet(12/20 Pages) PHILIPS

12 / 20 page

1996 Dec 20

Philips Semiconductors

Product speciﬁcation

Analog voice scrambler/descrambler

PCD4440T

Table 2

Explanation of time symbols used in Fig.10

SYMBOL

PARAMETER

DESCRIPTION

MIN.

MAX.

UNITS

fSCL

SCL clock frequency

100

kHz

tSW

tolerable pulse spike width

−

100

tBUF

bus free time

The time that the bus is free (SDA is HIGH)

before a new transmission is initiated by

SDA going LOW.

4.7

−µs

tSU;STA

set-up time repeated START

Only valid for repeated start code.

4.7

−µs

tHD;STA

hold time START condition

The time between SDA going LOW and the

ﬁrst valid negative-going transition of SCL.

4.0

−µs

tLOW

SCL LOW time

The LOW period of the SCL clock.

4.7

−µs

tHIGH

SCL HIGH time

The HIGH period of the SCL clock.

4.0

−µs

rise time SDA and SCL

−

1.0

µs

fall time SDA and SCL

−

0.3

µs

tSU;DAT

data set-up time

250

−

tHD;DAT

data hold time

−

tSU;STO

set-up time STOP condition

4.0

−µs

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