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AT25FS040

5107D–SFLSH–09/06

READ (READ): The READ instruction sequence reads the memory array up to the max-

imum speed of 50MHz. Reading the AT25FS040 via the SO (Serial Output) pin requires

the following sequence. After the CS line is pulled low to select the device, the READ

instruction is clocked in on the SI line, followed by the byte address to be read. Upon

completion, any data on the SI line will be ignored. The data (D7-D0) at the specified

address is then shifted out onto the SO line (see Figure 8). If only one byte is to be read,

the CS line should be driven high after the least significant data bit. To continue read

operation and sequentially read subsequent byte addresses from the device by simply

keeping CS low and provide a clock signal. The device incorporates an internal address

counter that automatically increments to the next byte address during sequential read

operation. The READ instruction can be continued since the byte address is automati-

cally incremented and data will continue to be shifted out of the AT25FS040 until the

highest byte address is reached. When the last bit of the memory has been read, the

device will continue reading back at the beginning of the array (000000h) without delay.

The data is always output from the device with the most significant bit (MSB) of a byte

first. The READ sequence is terminated any time CS is driven high and the device will

go into standby mode.

FAST READ (FAST READ): The FAST READ instruction sequence reads the memory

array up to the maximum speed of 50MHz (same as standard READ sequence). The

FAST READ is an alternate command for the READ and allows for FAST READ instruc-

tion compatibility support. The difference between the two is FAST READ requires a

“dummy byte” and READ does not. Reading the AT25FS040 via the SO (Serial Output)

pin requires the following sequence. After the CS line is pulled low to select the device,

the FAST READ instruction is clocked in on the SI line, followed by the byte address to

be read and the dummy byte (the SO line output will be high Z state). Upon completion,

any data on the SI line will be ignored. The data (D7-D0) at the specified address is then

shifted out onto the SO line (see Figure 9). If only one byte is to be read, the CS line

should be driven high after the least significant data bit. To continue read operation and

sequentially read subsequent byte addresses from the device by simply keeping CS low

and provide a clock signal. The device incorporates an internal address counter that

automatically increments to the next byte address during sequential read operation. The

FAST READ instruction can be continued since the byte address is automatically incre-

mented and data will continue to be shifted out of the AT25FS040 until the highest

address is reached. When the last bit of the memory has been read, the device will con-

tinue reading back at the beginning of the array (000000h) without delay. The data is

always output from the device with the most significant bit (MSB) of a byte first. The

FAST READ sequence is terminated any time CS is driven high and the device will go

into standby mode.

PROGRAM (PROGRAM): The PROGRAM instruction allows up to 256 data bytes to be

written to each page in the memory in one-operation changing data bits from a logic 1 to

0 state. The AT25FS040 memory array contains 524,288 programmable data bytes

internally organized into 256 bytes per page with a total of 2048 pages in the memory.

In order to program the AT25FS040, two separate instructions must be executed. First,

the device must be write enabled via the WREN instruction. Then the PROGRAM

instruction can be executed and requires the following sequence. After the CS line is

pulled low to select the device, the PROGRAM instruction is clocked in via the SI line

followed by the byte address (see Figure 10) and the data byte(s) to be programmed.

Programming will start after CS pin is brought high. Please note: The low to high transi-

tion of the CS pin must occur during the SCK low time immediately after clocking in the

D0 (LSB) data bit to initiate programming cycle. Also, a WREN instruction must precede

each and every PROGRAM instruction. The Ready/Busy status of the device can be

determined by initiating a RDSR instruction. If bit 0=1, the program cycle is still in