TSL2520 datasheet(33/69 Pages) OSRAM

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[v3-00] 2022-Dec-20

TSL2520 − Register O ver view

CFG4 Register

Figure 41:

CFG4

Note(s):

1. Return to the Register Map (0xA5).

Addr: 0xA5

CFG4

Bit

Field

Reset

Type

Bit Description

7Reserved

MOD_CALIBRATION_

NTH_ITERATION_

STEP_ENABLE

0R/W

Enable a modulator calibration with nth iterations

per sequencer step instead of waiting for a full round

for all sequencers to be finished. In case of AGC

enabled (MOD_CALIB_NTH_ITERATION_AGC_

ENABLE) this bit must be set “0”, otherwise AGC will

not properly work.

MEASUREMENT_

SEQUENCER_AGC_

PREDICT_TARGET_

LEVEL

0R/W

Sets the target measurement levels for AGC

prediction.

0: 50% of max value

1: 25% of max value

MEASURMENT_

SEQUENCER_

SINT_PER_STEP

0R/W

Invokes the system interrupt SINT_MEASUREMENT_

SEQUENCER per sequencer step instead of after a full

sequencer round.

OSC_TUNE_NO_

RESET

0R/W

OSC_TUNE is set to “0” at each transition of PON

from “0” to “1”. If OSC_TUNE_NO_RESET is asserted,

OSC_TUNE is not reset to “0”.

2:0

Reserved

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