TSL2520 datasheet(52/69 Pages) OSRAM

52 / 69 page

Datasheet, Public

Page 51

[v3-00] 2022-Dec-20

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TSL2520 − Register Overview

MOD_CALIB_CFG2 Register

Figure 69:

MOD_CALIB_CFG2

Note(s):

1. Return to the Register Map (0xE6).

VSYNC Period Registers

Figure 70:

VSYNC Period

Note(s):

1. Return to the Register Map (0xF2, 0xF3).

Addr: 0xE6

MOD_CALIB_CFG2

Bit

Field

Reset

Type

Bit Description

MOD_CALIB_NTH_

ITERATION_RC_

ENABLE

1R/W

Enables a residual calibration during the nth

iteration. Please observe that this residual calibration

feature only makes sense for modulators which are

enabled in the first sequences step, since a gain

calibration only happens in the first sequencer step.

MOD_CALIB_NTH_

ITERATION_AZ_

ENABLE

1R/W

Enables auto-zero calibration during the nth

iteration.

MOD_CALIB_NTH_

ITERATION_AGC_

ENABLE

0R/W

Enables AGC calibration during the nth iteration.

Please observe in this case, that MOD_CALIB_NTH_

ITERATION_STEP_ENABLE must be “0” otherwise

AGC will not be properly executed.

MOD_CALIB_

RESIDUAL_ENABLE_

AUTO_CALIB_ON_

GAIN_CHANGE

1R/W

Enables an automatic re-calibration in case of a

change in gain. This re-calibration is executed at the

beginning of each sequencer step.

3:0

Reserved

0x3

Addr

Bit

Field

Reset

Type

Description

0xF2

7:0

VSYNC_PERIOD[7:0]

0R/W

VSYNC Period

Contains the measured VSYNC in

multiples of 1.3888μs Reading this

0xF3

7:0

VSYNC_PERIOD[15:8]

0R/W

TSL2520 Datasheet(PDF) 52 Page - OSRAM GmbH

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