MSC8144 datasheet(39/80 Pages) FREESCALE

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Electrical Characteristics

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

Freescale Semiconductor

See also Reset Errata for PLL lock and reset duration.

2.7.4

DDR SDRAM AC Timing Specifications

This section describes the AC electrical characteristics for the DDR SDRAM interface.

2.7.4.1

DDR SDRAM Input Timings

Table 22 provides the input AC timing specifications for the DDR SDRAM when VDD(typ) = 2.5 V.

Table 23 provides the input AC timing specifications for the DDR SDRAM when VDD(typ) = 1.8 V.

Table 24 provides the input AC timing specifications for the DDR SDRAM interface.

Figure 8. Timing for a Reset Configuration Write

Table 22. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

Parameter

Symbol

Min

Max

Unit

AC input low voltage

VIL

—MVREF – 0.31

AC input high voltage

VIH

MVREF + 0.31

—

Note:

At recommended operating conditions with VDD of 2.5 ± 5%.

Table 23. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

Parameter

Symbol

Min

Max

Unit

AC input low voltage

VIL

—VREF – 0.25

AC input high voltage

VIH

VREF + 0.25

—

Note:

At recommended operating conditions with VDD of 1.8 ± 5%.

Table 24. DDR SDRAM Input AC Timing Specifications

Parameter

Symbol

Min

Max

Unit

Controller Skew for MDQS—MDQ/MECC/MDM1

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tCISKEW

–365

–390

–428

–490

365

390

428

490

Notes:

tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is

captured with MDQS[n]. Subtract this value from the total timing budget.

At recommended operating conditions with VDD (1.8 V or 2.5 V) ± 5%

PORESET

HRESET

Input

Output (I/O)

SRESET

Output (I/O)

RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG

pins must be valid

Reset configuration write

sequence during this

period.

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