MSC8144 datasheet(73/80 Pages) FREESCALE

73 / 80 page

Hardware Design Considerations

MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1

Freescale Semiconductor

3.3.4.3

GE1 and GE2 Management Pins

GE_MDC and GE_MDIO pins should be connected as required by the specified protocol. If neither GE1 nor GE2 is used (that

is, VDDGE2 is connected to GND), Table 64 lists the recommended management pin connections.

3.3.5

UTOPIA Related Pins

Table 65 lists the board connections of the UTOPIA pins when the entire UTOPIA interface is not used or subset of UTOPIA

interface is used. For multiplexing options that select a subset of the UTOPIA interface, use the connections described in

Table 65 for those signals that are not selected. Table 65 assumes that the alternate function of the specified pin is not used. If

the alternate function is used, connect that pin as required to support the selected function.

GE2_SGMII_RX

GNDSXC

GE2_SGMII_TX

GE2_TCK

GE2_TD[0–3]

GE2_TX_EN

Table 64. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used

Signal Name

Pin Connection

GE_MDC

GE_MDIO

Table 65. Connectivity of UTOPIA Related Pins When UTOPIA Interface Is Not Used

Signal Name

Pin Connection

UTP_IR

GND

UTP_RADDR[0–4]

VDDIO

UTP_RCLAV_PDRPA

UTP_RCLK

GND

UTP_RD[0–15]

GND

UTP_REN

VDDIO

UTP_RPRTY

GND

UTP_RSOC

GND

UTP_TADDR[0–4]

VDDIO

UTP_TCLAV

UTP_TCLK

GND

UTP_TD[0–15]

UTP_TEN

VDDIO

UTP_TPRTY

UTP_TSOC

VDDIO

3.3 V

Table 63. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)

Signal Name

Pin Connection

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