JTAG Timing

56F802 Technical Data, Rev. 9

Freescale Semiconductor

29

1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at

sampling time. (1pf)

Figure 3-13 Equivalent Analog Input Circuit

3.10 JTAG Timing

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz

operation, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Parameters listed are guaranteed by design.

DC

10

MHz

TCK cycle time

100

—

ns

TCK clock pulse width

50

—

ns

TMS, TDI data setup time

0.4

—

ns

TMS, TDI data hold time

1.2

—

ns

TCK low to TDO data valid

—

26.6

ns

TCK low to TDO tri-state

—

23.5

ns

TRST assertion time

50

—

ns

1

2

3

4

ADC analog input