DSP56F802 datasheet(36/40 Pages) FREESCALE

36 / 40 page

56F802 Technical Data, Rev. 9

Freescale Semiconductor

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Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)

pins are less than 0.5 inch per capacitor lead.

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Bypass the VDD and VSS layers of the PCB with approximately 100 μF, preferably with ceramic or tantalum

capacitors which tend to provide better performance tolerances.

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Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

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Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the VDD and GND circuits.

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Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.

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Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or

debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means

to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs

that do not require debugging functionality, such as consumer products, TRST should be tied low.

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Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an

interface to this port to allow in-circuit Flash programming.

DSP56F802 Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc