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DSP56F802 Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc |
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DSP56F802 Datasheet(HTML) 17 Page - Freescale Semiconductor, Inc |
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17 / 40 page ![]() DC Electrical Characteristics 56F802 Technical Data, Rev. 9 Freescale Semiconductor 17 Output Low Voltage (at IOL) VOL — — 0.4 V Output source current IOH 4 — — mA Output sink current IOL 4 — — mA PWM pin output source current3 IOHP 10 — — mA PWM pin output sink current4 IOLP 16 — — mA Input capacitance CIN — 8 — pF Output capacitance COUT — 12 — pF VDD supply current IDDT5 Run6 (80MHz Operation) — 120 130 mA Run6 (60MHz Operation) — 102 111 mA Wait7 — 96 102 mA Stop — 62 70 mA Low Voltage Interrupt, external power supply8 VEIO 2.4 2.7 3.0 V Low Voltage Interrupt, internal power supply9 VEIC 2.0 2.2 2.4 V Power on Reset10 VPOR — 1.7 2.0 V 1. Schmitt Trigger inputs are: FAULTA0, TCS, TCK, TMS, TDI, RESET, and TRST 2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling. 3. PWM pin output source current measured with 50% duty cycle. 4. PWM pin output sink current measured with 50% duty cycle. 5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured with PLL enabled. 8. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated). 9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V). Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit |
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