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M68HC05 Datasheet(PDF) 104 Page - Freescale Semiconductor, Inc |
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M68HC05 Datasheet(HTML) 104 Page - Freescale Semiconductor, Inc |
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104 / 118 page  Electrical Specifications MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 104 Freescale Semiconductor Figure 12-9. SPI Master Timing Diagram NOTE Note: SS pin of master held high. MSB IN SS (INPUT) SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) MOSI (OUTPUT) NOTE 4 5 5 1 13 12 4 12 13 BIT 6–1 LSB IN MASTER MSB OUT BIT 6–1 MASTER LSB OUT 10 (ref) 13 11 10 12 11 (ref) 7 6 NOTE Note: SS pin of master held high. MSB IN SS (INPUT) SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) MOSI (OUTPUT) NOTE 4 5 5 1 13 12 4 13 BIT 6–1 LSB IN MASTER MSB OUT BIT 6–1 MASTER LSB OUT 10 (ref) 13 11 10 12 11 7 6 12 a) SPI Master Timing (CPHA = 0) b) SPI Master Timing (CPHA = 1) 12 This first clock edge is generated internally, but is not seen at the SCK pin. This last clock edge is generated internally, but is not seen at the SCK pin. |
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