Analog Integrated Circuit Device Data

26

Freescale Semiconductor

34921

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

frame (refer to Table 11, page 28).

Three different types of conversion can occur (refer to

Table 7):

• Single Conversion 00X does a single conversion of

inputs AN0/ANALOGOUT_A or AN1/ANALOGOUT_B.

• Double Conversion 1XX does a double conversion of

AN2/ANALOGIN_A and AN3/ANALOGIN_B,

respectively.

• Auto-Select Conversion 011 does a single

conversion of one of the outputs from the analog

encoder interface, as selected by the digital outputs of

the analog encoder interface, DENCA and DENCB.

Table 7. A/D Input Conversion Channel Addressing

A/D Conversion Flow

There is a START conversion bit in the serial channel. The

presence of this bit begins a conversion cycle on the input(s)

selected in that frame. If the ADC is converting when a

subsequent START bit arrives, this start request will be

ignored. Figure 14, A/D Converter Input Structure, page 27,

shows how this process works. The current conversion

completes during the frame prior to the data being returned.

If there is a START bit in that input frame, another conversion

is begun as the previous conversion’s data is being shifted

out. If there is no START bit in the input frame, then another

conversion is begun the frame following receipt of the start

bit. The single conversion rate is paced at four frames for

configuration bit 3 =0 or eight frames (or less) for

configuration bit 3 =1, including sampling time (refer to

Table 13, CONFIG Input Frame Bit Allocation, page 29). In

order to simplify implementation of the 34921, the user must

ensure that no A/D conversions are in progress when an

INFO word is requested. For input pairs, the inputs are listed

in the order of conversion in Table 7.

NORMAL

Input

Frame

Bit 2

NORMAL

Input

Frame

Bit 3

NORMAL

Input

Frame

Bit 4

NORMAL

Output

Frame

Bit 2(27)

NORMAL

Output

Frame

Bit 3(27)

Input(s) Selected

A/Da0

A/Da1

A/Da2

DENCA

DENCB

0

0

0

X

X

AN0/ANALOGOUT_A terminal

1

00X

X

AN1/ANALOGOUT_B terminal

11

0

1

0

Analog encoder interface output A

11

0

0

1

Analog encoder interface output A

11

0

1

1

Analog encoder interface output B

11

0

0

0

Analog encoder interface output B

1

01X

X

Analog encoder interface outputs A and A with S/H (28)

0

01X

X

Analog encoder interface outputs A and B with S/H (28)

0

11X

X

Analog encoder interface outputs B and B with S/H (28)

1

11X

X

AN2/ANALOGIN_A and AN3/ANALOGIN_B terminals (direct input) with

S/H (28)

Notes

Notes

27.

DENCA and DENCB values are captured at the output of the 3 or 6 Edge filter on SCLK rising edge, then immediately

shifted out in the MISO data when CE is high.

28.

Inputs are listed in order of conversion.