34921 datasheet(27/36 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34921

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

A/D Converter Input Structure

The input impedance of a selected channel is an RC

circuit. As shown in Figure 14, the input impedance of the

selected channel is a resistor connected to the sample and

hold (S/H) capacitor. The sample and hold time is 15 * tSCLK,

or a minimum of 0.9285

µs. The tolerances of the internal S/

H components are such that a time constant is about 93.6 ns.

Therefore to achieve a proper level on the S/H capacitor

(5*93.6 ns) = 0.468

µs, minimum, is required to satisfy

internal component time constants. This only allows 460 ns

for external time constants. Therefore, the maximum source

impedance of the circuit driving the selected A/D channel is

7.8 k

Ω when the SCLK speed matches the speed

configuration bit.

Figure 14. A/D Converter Input Structure

ADC Output Addressing

The return word to the digital subsystem also contains two

conversion done bits, A/Ddone1 and A/Ddone2 (refer to

Table 8). The A/Ddone1 bit is used for single conversions

and the first conversion when input pairs are selected. The

A/Ddone2 bit is used for the second conversion when input

pairs are selected. A zero to one transition of these bits on

successive return words indicates that a conversion cycle is

complete and the data sent in that return word is valid for that

conversion. The conversion done bits will only be asserted for

one serial frame, although the data may be valid for multiple

frames. The A/Dr bits indicate which A/D input is being

reported when data is valid (refer to Table 9).

Idle

A2Ddone1=0

A/Da=Last Address

A/Dd=Last

Conversion

Start

A2Ddone2=0

Conversion

Convert

A2Ddone1=0

A/Da=Current

A/Dd=Last

A2Ddone2=0

Conversion

Start

Done

A/Da=1

Start

Conversion

Done

Address

Send Data

A2Ddone1=0

A2Da=Current

A2Dd=Current

A2Ddone2=0

Conversion

Address

Convert2

A2Ddone1=0

A/Da=Current

A/Dd=Last

A2Ddone2=0

Conversion

Address

Send Data2

A2Ddone1=0

A/Da=Current

A/Dd=Current

A2Ddone2=1

Conversion

Address

Note “Start” is bit 1 of the serial input normal frame.

Table 8. A/D Done Bits

A/Ddone1

A/Ddone2

Return Data and A/Dr Value

Rising

Valid for single or first conversion

Rising

Valid for second conversion

Don’t care

Table 9. A/D Channel of Current A/D Data

NORMAL

Output

Frame

Bit 4

NORMAL

Output

Frame

Bit 5

NORMAL

Output

Frame

Bit 6

A/D Value Reported

A/Dr0

A/Dr1

A/Dr2

AN0/ANALOGOUT_A

AN1/ANALOGOUT_B

AN2/ANALOGIN_A

(direct input)

AN3/ANALOGIN_B

(direct input)

I/V

Channel Select Logic

S/H

C < 11.7 pF

hold

SCLK

AN0/ANALOGOUT_A

AN1/ANALOGOUT_B

AN2/ANALOGIN_A

AN3/ANALOGIN_B

Multiplexer RDS(on) < 8.0 kΩ

34921 Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc

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