Data Sheet

AD5122A/AD5142A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. D | 11 of 29

Figure 4. 16-Lead LFCSP Pin Configuration

Figure 5. 16-Lead TSSOP Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

16-Lead

LFCSP

16-Lead

TSSOP

1

3

GND

Ground Pin, Logic Ground Reference.

2

4

A1

Terminal A of RDAC1. VSS ≤ VA ≤ VDD.

3

5

W1

Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.

4

6

B1

Terminal B of RDAC1. VSS ≤ VB ≤ VDD.

5

7

VSS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

6

8

A2

Terminal A of RDAC2. VSS ≤ VA ≤ VDD.

7

9

W2

Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.

8

10

B2

Terminal B of RDAC2. VSS ≤ VB ≤ VDD.

9

11

VDD

Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

10

12

VLOGIC

Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

11

13

SCL

Serial Clock Line.

12

14

SDA

Serial Data Input/Output.

13

15

ADDR1

Programmable Address (ADDR1) for Multiple Package Decoding.

14

16

ADDR0

Programmable Address (ADDR0) for Multiple Package Decoding.

15

1

INDEP

Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location. If INDEP is enabled,

it cannot be disabled by the software.

16

2

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at logic low. If this pin is not used, tie

RESET to VLOGIC.

EPAD

Exposed Pad. Connect this exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is

recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.