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AD5142ABCPZ10-RL7 Datasheet(PDF) 23 Page - Analog Devices |
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AD5142ABCPZ10-RL7 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 29 page ![]() Data Sheet AD5122A/AD5142A THEORY OF OPERATION analog.com Rev. D | 23 of 29 Table 14. Address Bits A3 A2 A1 A0 Potentiometer Mode Linear Gain Setting Mode Stored Channel Memory Input Register RDAC Register Input Register RDAC Register 1 X1 X1 X1 All channels All channels All channels All channels Not applicable 0 0 0 0 RDAC1 RDAC1 RWB1 RWB1 RDAC1/RWB1 0 1 0 0 Not applicable Not applicable RAW1 RAW1 Not applicable 0 0 0 1 RDAC2 RDAC2 RWB2 RWB2 RAW1 0 1 0 1 Not applicable Not applicable RAW2 RAW2 Not applicable 0 0 1 0 Not applicable Not applicable Not applicable Not applicable RDAC2/RWB2 0 0 1 1 Not applicable Not applicable Not applicable Not applicable RAW2 1 X = don’t care. Table 15. Control Register Bit Descriptions Bit Name Description D0 RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) D1 EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) D2 Linear setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode D3 Burst mode (I2C only) 0 = disabled (default) 1 = enabled (no disable after stop or repeated start condition) |
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