AD5142ABCPZ10-RL7 datasheet(25/29 Pages) AD

25 / 29 page

Data Sheet

AD5122A/AD5142A

THEORY OF OPERATION

analog.com

Rev. D | 25 of 29

Table 18. Detailed Left Shift and Right Shift Functions for the ±6 dB Step

Increment and Decrement (Continued)

Left Shift (+6 dB/Step)

Right Shift (−6 dB/Step)

0001 0000

0000 0111

0010 0000

0000 0011

0100 0000

0000 0001

1000 0000

0000 0000

1111 1111

0000 0000

Burst Mode

By enabling the burst mode, multiple data bytes can be sent to the

part consecutively. After the command byte, the part interprets the

following consecutive bytes as data bytes for the command.

A new command can be sent by generating a repeat start or by a

stop and start condition.

The burst mode is activated by setting Bit D3 of the control register

(see Table 15).

Reset

The AD5122A/AD5142A can be reset through software by execut-

ing Command 14 (see Table 13) or through hardware on the low

pulse of the RESET pin. The reset command loads the RDAC reg-

isters with the contents of the EEPROM and takes approximately

30 µs. The EEPROM is preloaded to midscale at the factory, and

initial power-up is, accordingly, at midscale. Tie RESET to VLOGIC if

the RESET pin is not used.

Shutdown Mode

The AD5122A/AD5142A can be placed in shutdown mode by exe-

cuting the software shutdown command, Command 15 (see Table

13), and setting the LSB (D0) to 1. This feature places the RDAC

in a zero power consumption state where the device operates in

potentiometer mode, Terminal A is open-circuited and the wiper,

Terminal W, is connected to Terminal B; however, a finite wiper

resistance of 40 Ω is present. When the device is configured in

linear gain setting mode, the resistor addressed, RAW or RWB,

is internally placed at high impedance. Table 19 shows the truth

table depending on the device operating mode. The contents of

the RDAC register are unchanged by entering shutdown mode.

However, all commands listed in Table 13 are supported while in

shutdown mode. Execute Command 15 (see Table 13) and set the

LSB (D0) to 0 to exit shutdown mode.

Table 19. Truth Table for Shutdown Mode

Linear Gain Setting Mode

Potentiometer Mode

RAW

RWB

RAW

RWB

High impedance

RBS

EEPROM OR RDAC REGISTER PROTECTION

The EEPROM and RDAC registers can be protected by disabling

any update to these registers. This can be done by using software.

If these registers are protected by software, set Bit D0 and/or Bit D1

(see Table 15), which protects the RDAC and EEPROM registers

independently.

When RDAC is protected, the only operation allowed is to copy the

EEPROM into the RDAC register.

INDEP PIN

If the INDEP pin is pulled high at power-up, the part operates in

linear gain setting mode, loading each string resistor, RAWX and

RWBX, with the value stored into the EEPROM (see Table 14). If the

pin is pulled low, the part powers up in potentiometer mode.

The INDEP pin and the D2 bit are connected internally to a logic

OR gate; if one or both are set to 1, the part cannot operate in

potentiometer mode (see Table 15).

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices, Inc., has propri-

etary RDAC segmentation architecture for all the digital potentiom-

eters. In particular, the AD5122A/AD5142A employ a three‑stage

segmentation approach, as shown in Figure 41. The AD5122A/

AD5142A wiper switch is designed with the transmission gate

CMOS topology and with the gate voltage derived from VDD and

VSS.

Figure 41. AD5122A/AD5142A Simplified RDAC Circuit

Top Scale/Bottom Scale Architecture

In addition, the AD5122A/AD5142A include new positions to re-

duce the resistance between terminals. These positions are called

bottom scale and top scale. At bottom scale, the typical wiper

resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ). At

top scale, the resistance between Terminal A and Terminal W is

decreased by 1 LSB, and the total resistance is reduced to 60 Ω

(RAB = 100 kΩ).

AD5142ABCPZ10-RL7 Datasheet(PDF) 25 Page - Analog Devices

AD5142ABCPZ10-RL7 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL