SCF5249LAG120 datasheet(4/56 Pages) FREESCALE

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SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

SCF5249 Feature Details

Freescale Semiconductor

•

DMA controller

— Four fully programmable channels: Two dedicated to the audio interface module and two

dedicated to the UART module (External requests are not supported.)

— Supports dual- and single-address transfers with 32-bit data capability

— Two address pointers that can increment or remain constant

— 16-/24-bit transfer counter

— Operand packing and unpacking support

— Auto-alignment transfers supported for efficient block movement

— Supports bursting and cycle stealing

— All channels support memory to memory transfers

— Interrupt capability

— Provides two clock cycle internal access

•

Enhanced Multiply-accumulator Unit

— Single-cycle multiply-accumulate operations for 32 x 32 bit and 16 x 16 bit operands

— Support for signed, unsigned, integer, and fixed-point fractional input operands

— Four 48-bit accumulators to allow the use of a 40-bit product

— The addition of 8 extension bits to increase the dynamic number range

— Fast signed and unsigned integer multiplies

•

8-KByte Direct Mapped instruction cache

— Clock-doubled to match microprocessor core speed

— Flush capability

— Non-blocking cache provides fast access to critical code and data

•

96-KByte SRAM

— Provides one-cycle access to critical code and data

— Split into two banks, SRAM0 (32K), and SRAM1 (64K)

— DMA requests to/from internal SRAM1 supported

•Crystal Trim

— The XTRIM output can be used to trim an external crystal oscillator circuit which would

allow lock with an incoming IEC958 or serial audio signal

•

Audio Interfaces

— IEC958 input and output

— Four serial Philips IIS/Sony EIAJ interfaces

– One with input and output, one with output only, two with input only (Three inputs, two

outputs)

– Master and Slave operation

SCF5249LAG120 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc

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