SCF5249LAG120 datasheet(7/56 Pages) FREESCALE

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SCF5249 Functional Overview

SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Freescale Semiconductor

SCF5249 Functional Overview

5.1

ColdFire V2 Core

The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to

maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage

pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage

operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then

executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer

that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,

which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline

featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit

(ALU).

5.2

DMA Controller

The SCF5249 provides four fully programmable DMA channels for quick data transfer. Single and dual

address mode is supported with the ability to program bursting and cycle stealing. Data transfer is

selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.

Table 2. 160 MAPBGA Ball Assignments

160 MAPBGA

Ball Number

Function

GPIO

cmd_sdio2

gpio34

sdata0_sdio1

gpio54

RSTO/sdata2_bs2

A25

gpo8

QSPI_CS1

gpio24

QSPI_CS3

gpio22

SDRAM_CS2

gpio7

EbuOut2

gpo 37

K11

BUFENb2

gpio17

G12

subr

gpio 53

F13

sfsy

gpio 52

F12

rck

gpio 51

SRE

gpio11

lrck3

gpio 45

SWE

gpio12

sclk3

gpio 49

SCF5249LAG120 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

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