SCF5249LAG120 datasheet(6/56 Pages) FREESCALE

6 / 56 page

SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

160 MAPBGA Ball Assignments

Freescale Semiconductor

•

System debug support

— Real-time instruction trace for determining dynamic execution path

— Background debug mode (BDM) for debug features while halted

— Debug exception processing capability

— Real-time debug support

•

System Interface

— Glueless bus interface with four chip selects and DRAMC support for interface to

16-bit for DRAM, SRAM, ROM, FLASH, and I/O devices

– Two programmable chip-select signals for static memories or peripherals, with

programmable wait states and port sizes.

– Two dedicated chip selects for 16-bit wide DRAM /SDRAM.

– CS0 is active after reset to provide boot-up from external FLASH/ROM.

— Programmable interrupt controller

– Low interrupt latency

– Eight external interrupt requests

– Programmable autovector generator

— 44 programmable general-purpose inputs*

— 46 programmable general-purpose outputs*

– * For the 160 MAPBGA package

— IEEE 1149.1 Test (JTAG) Module

•

Clocking

— Clock-multiplied PLL, programmable frequency

•

1.8V Core, 3.3V I/O

•

160 pin MAPBGA package (qualified at 140 MHz) and 144 pin QFP package (qualified at 120

MHz)

160 MAPBGA Ball Assignments

The following signals are not available on the 144 QFP package.

NOTE

The 144 QFP part is qualified for 120 MHz operation. The 160MAPBGA

part is qualified for 140 MHz.

SCF5249LAG120 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc