CDCE949

CDCEL949

SCAS844 – JUNE 2007

Table 10. PLL1 Configuration Register

Acronym

DESCRIPTION

10h

7:5

SSC1_7 [2:0]

000b

4:2

SSC1_6 [2:0]

000b

Down

Center

000 (off)

000 (off)

1:0

SSC1_5 [2:1]

001 – 0.25%

001

± 0.25%

000b

010 – 0.5%

010

± 0.5%

11h

7

SSC1_5 [0]

011 – 0.75%

011

± 0.75%

6:4

SSC1_4 [2:0]

000b

100 – 1.0%

100

± 1.0%

101 – 1.25%

101

± 1.25%

3:1

SSC1_3 [2:0]

000b

110 – 1.5%

110

± 1.5%

0

SSC1_2 [2]

111 – 2.0%

111

± 2.0%

000b

12h

7:6

SSC1_2 [1:0]

5:3

SSC1_1 [2:0]

000b

2:0

SSC1_0 [2:0]

000b

13h

7

FS1_7

0b

6

FS1_6

0b

5

FS1_5

0b

4

FS1_4

0b

3

FS1_3

0b

2

FS1_2

0b

1

FS1_1

0b

0

FS1_0

0b

14h

PLL1 Multiplexer:

0 – PLL1

7

MUX1

1b

1 – PLL1 Bypass (PLL1 is in power down)

Output Y2 Multiplexer:

0 – Pdiv1

6

M2

1b

1 – Pdiv2

Output Y3 Multiplexer:

00 – Pdiv1-Divider

01 – Pdiv2-Divider

5:4

M3

10b

10 – Pdiv3-Divider

11 – reserved

3:2

Y2Y3_ST1

11b

Y2,

00 – Y2/Y3 disabled to 3-State (PLL1 is in power down)

Y3-State0/1definition:

01 – Y2/Y3 disabled to 3-State (PLL1 on)

10–Y2/Y3 disabled to low (PLL1 on)

1:0

Y2Y3_ST0

01b

11 – Y2/Y3 enabled (normal operation, PLL1 on)

15h

7

Y2Y3_7

0b

6

Y2Y3_6

0b

0 – state0 (predefined by Y2Y3_ST0)

1 – state1 (predefined by Y2Y3_ST1)

5

Y2Y3_5

0b

4

Y2Y3_4

0b

3

Y2Y3_3

0b

2

Y2Y3_2

0b

1

Y2Y3_1

1b

0

Y2Y3_0

0b

16h

PLL1 SSC down/center selection:

0 – down

7

SSC1DC

0b

1 – center

7-Bit Y2-Output-Divider Pdiv2:

0 – reset and stand-by

6:0

Pdiv2

01h

1-to-127 – divider value

17h

7

—

0b

Reserved – do not write others than 0

7-Bit Y3-Output-Divider Pdiv3:

0 – reset and stand-by

6:0

Pdiv3

01h

1-to-127 – divider value

(1)

Writing data beyond 50h may adversely affect device function.

(2)

All data is transferred MSB-first.

(3)

Unless a custom setting is used

(4)

The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external

control pins, S0, S1, and S2.

17

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