CDCE949 datasheet(25/31 Pages) TI

25 / 31 page

PLL MULTIPLIER/DIVIDER DEFINITION

OUT +

Pdiv

VCO + ƒIN

)

int(log

{if P < 0 then P = 0}

)

int(

Q =

CDCE949

CDCEL949

SCAS844 – JUNE 2007

At a given input frequency (fIN), the output frequency (fOUT) of the CDCE949/CDCEL949 can be calculated by:

where

M (1 to 511) and N (1 to 4095) are the multiplier/divider values of the PLL;

Pdiv (1 to 127) is the output divider.

The target VCO frequency (fVCO) of each PLL can be calculated:

The PLL operates as fractional divider and needs following multiplier/divider settings

Where:

N’ = N

× 2P;

≥ M;

80 MHz < fVCO > 230 MHz.

Example 1: for fIN = 27 MHz; M = 1; N = 4; Pdiv = 2;

Example 2: for fIN = 27 MHz; M = 2; N = 11; Pdiv = 2;

→ f

OUT = 54 MHz;

→ f

OUT = 75.25 MHz;

→ f

VCO = 108 MHz;

→ f

VCO = 148.50 MHz;

→ P = 4 – int(log

24) = 4 –2 = 2;

→ P = 4 – int(log

25.5) = 4 – 2 = 2;

→ N’ = 4 × 22 = 16;

→ N’ = 11 × 22 = 44;

→ Q = int(16) = 16;

→ Q = int(22) = 22;

→ R = 16 – 16 = 0;

→ R = 44 – 44 = 0;

The values for P, Q, R and N’ are automatically calculated when using TI Pro Clock™ Software.

Submit Documentation Feedback

CDCE949 Datasheet(PDF) 25 Page - Texas Instruments

CDCE949 Datasheet(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL