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4571 Datasheet(PDF) 65 Page - Renesas Technology Corp |
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4571 Datasheet(HTML) 65 Page - Renesas Technology Corp |
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65 / 126 page  Rev.1.02 May 25, 2007 Page 65 of 124 REJ03B0179-0102 4571 Group Note 1.“R” represents read enabled, and “W” represents write enabled. Clock control register MR at reset : 11112 at RAM back-up : 11112 R/W TAMR/TMRA Operation mode selection bits MR3 MR2 Operation mode MR3 0 0 Through mode (frequency not divided) 0 1 Frequency divided by 2 mode 1 0 Frequency divided by 4 mode MR2 1 1 Frequency divided by 8 mode MR1 Not used 0 This bit has no function, but read/write is enabled. 1 MR0 Not used 0 This bit has no function, but read/write is enabled. 1 Key-on wakeup control register K0 at reset : 00002 at RAM back-up : state retained R/W TAK0/TK0A K03 Port P03 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K02 Port P02 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K01 Port P01 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K00 Port P00 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used Key-on wakeup control register K1 at reset : 00002 at RAM back-up : state retained R/W TAK1/TK1A K13 Port P13 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K12 Port P12 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K11 Port P11 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K10 Port P10 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used Key-on wakeup control register K2 at reset : 00002 at RAM back-up : state retained R/W TAK2/TK2A K23 Not used 0 This bit has no function, but read/write is enabled. 1 K22 Port K key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K21 Port P21 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used K20 Port P20 key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used Key-on wakeup control register L1 at reset : 00002 at RAM back-up : state retained R/W TAL1/TL1A L13 INT1 pin return condition selection bit 0 Return by level 1 Return by edge L12 INT1 pin valid waveform/ level selection bit 0 Falling waveform/“L” level 1 Rising waveform/“H” level L11 INT0 pin return condition selection bit 0 Return by level 1 Return by edge L10 INT0 pin key-on wakeup control bit 0 Key-on wakeup not used 1 Key-on wakeup used |
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