Power Dissipation (W)

0

0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27

0.3

55

60

65

70

75

80

85

90

95

100

105

110

115

120

125

D028

TLV743P DQN, High-K Layout

TLV743P DBV, High-K Layout

D

IN

OUT

OUT

3

9

± 9

,

u

17

TLV743P

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SBVS310C – JULY 2017 – REVISED JUNE 2019

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Application Information (continued)

8.1.3 Power Dissipation

The ability to remove heat from the die is different for each package type and presents different considerations in

the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves

the heat from the device to ambient air. Performance data for JEDEC high-K boards are shown in Thermal

Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of

plated through-holes to heat-dissipating layers also improves heat sink effectiveness.

Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output

current and voltage drop across the output pass element, as shown in Equation 2.

(2)

Figure 31 shows the maximum ambient temperature versus the power dissipation of the TLV743P device in the

DQN and DBV packages. This figure assumes the device is soldered on JEDEC standard high-K layout with no

airflow over the board. Actual board thermal impedances vary widely. If the application requires high power

dissipation, it is helpful to have a thorough understanding of the board temperature and thermal impedances to

make certain that the TLV743P device does not operate continuously above a junction temperature of 125°C.

TLV743P, high-K layout

Figure 31. Maximum Ambient Temperature vs Device Power Dissipation