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MB95F104AJS Datasheet(PDF) 49 Page - fujitsu semiconductor |
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MB95F104AJS Datasheet(HTML) 49 Page - fujitsu semiconductor |
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49 / 72 page ![]() MB95100AM Series 49 (6) UART/SIO, Serial I/O Timing (Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C) * : Refer to “ (2) Source Clock/Machine Clock” for tMCLK. Parameter Symbol Pin name Conditions Value Unit Min Max Serial clock cycle time tSCYC UCK0 Internal clock operation 4 tMCLK* ⎯ ns UCK ↓ → UO time tSLOV UCK0, UO0 − 190 + 190 ns Valid UI → UCK ↑ tIVSH UCK0, UI0 2 tMCLK* ⎯ ns UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 tMCLK* ⎯ ns Serial clock “H” pulse width tSHSL UCK0 External clock operation 4 tMCLK* ⎯ ns Serial clock “L” pulse width tSLSH UCK0 4 tMCLK* ⎯ ns UCK ↓ → UO time tSLOV UCK0, UO0 ⎯ 190 ns Valid UI → UCK ↑ tIVSH UCK0, UI0 2 tMCLK* ⎯ ns UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 tMCLK* ⎯ ns tSCYC tIVSH 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSHIX tSLOV 0.8 V 2.4 V 0.8 V 2.4 V UCK0 UO0 UI0 0.8 V tSLSH tIVSH tSHIX tSLOV 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC tSHSL 2.4 V UCK0 UO0 UI0 0.8 V 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC • Internal shift clock mode • External shift clock mode |
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