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MB90583CAPF Datasheet(PDF) 23 Page - fujitsu semiconductor |
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MB90583CAPF Datasheet(HTML) 23 Page - fujitsu semiconductor |
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23 / 110 page ![]() MB90580C Series 23 s BLOCK DIAGRAM X0, X1 X0A, X1A RST HST 6 8 3 3 8 8 3 P00 to P07/ AD00 to AD07 P10 to P17/ AD08 to AD15 P20 to P27/ A16 to A23 P30/ALE P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P47 SIN0, SOT0, SCK0/ P40 to P42 3 8 8 SIN1, SOT1, SCK1/ P43 to P45 P90 to P92/ TIN0 to TIN2/ IN0 to IN2 2 P94, P95/ TOT1, TOT2/ OUT0, OUT1 2 2 P63, P64/ PPG1, PPG0 3 SIN2, SOT2, SCK2/ P60 to P62 8 P80 to P87/ IRQ0 to IRQ7 2 P71, P72 2 P73, P74 /DA00, DA01 P93/ TOT0/ IN3 PA0 to PA2 P96/PWC P97/POT P65/CKOT DVRH DVSS ADTG / P46 AVCC AVRH, AVRL AVSS SIN3, SOT3, SCK3/ P50 to P52/ AN0 to AN2 P53/AN3, P57/AN7 SIN4, SOT4, SCK4/ P54 to P56/ AN4 to AN6 TX RX ROM UART × 2 ch UART × 1 ch 8 / 16 PPG × 1 ch UART × 2 ch RAM * Other pins MD2 to MD0 C,VCC,VSS 3 3 2 Clock control circuit CMOS I/O port 0 CMOS I/O port 1 CMOS I/O port 2 CMOS I/O port 3 Prescaler × 2 ch A/D converter (8/10 bit) Interrupt controller CMOS I/O port A CMOS I/O port 9 CMOS I/O port 8 CMOS I/O port 7 External interrupt D/A converter (8 bit) × 2 ch Evaluation device (MB90V580B) This chip has no internal ROM. Internal RAM is 6 Kbytes. Internal resources are common. The package is PGA-256C-A02. IEBusTM controller Prescaler × 2 ch CMOS I/O port 6 CMOS I/O port 5 I/O timer 16 bit ICU × 4 ch 16 bit OCU × 2 ch 16 bit free run timer 16 bit reload timer × 3 ch Noise filter PWC timer 16 bit × 1 ch Prescaler × 1 ch P00 to 07 (8 channels): Provided with a register available as an input pull-up resistor. P10 to 17(8 channels): Provided with a register available as an input pull-up resistor. P60 to 65(6 channels): Provided with a register available as an input pull-up resistor. P40 to 47 (8 channels): Provided with a register available as an open drain. *: The MB90587C/CA has no IEBusTM controller. The TX and RX pins are N.C. pins. Clock monitor CPU Core of F2MC-16LX family |
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