TAS5815PWPR datasheet(40/123 Pages) TI

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2. Configure each device phase selection and enable the phase synchronization. For example: Register 0x6A

= 0x00 for device 0; Register 0x6A = 0x04 for device 1; Register 0x6A = 0x08 for device 2; Register 0x6A =

0x0C for device 3. There should be a 45 degree PWM phase shift between each device to minimize the EMI.

3. Configure each device into Hi-Z mode.

4. Provide I2S to each device. Phase synchronization for all 4 devices are automatically done by internal

sequence.

5. Initialize the DSP code. (This step can be skipped if only need to do the PWM Phase Synchronization).

6. Device to Device PWM phase shift should be fixed with 45 degree.

7.4.4 Thermal Foldback

The Thermal Foldback (TFB), is designed to protect TAS5815 from excessive die temperature increases, in case

the device operates beyond the recommended temperature/power limit, or with a weaker thermal system design

than recommended. It allows the TAS5815 to play as loud as possible without triggering unexpected thermal

shutdown. When the die temperature triggers the over-temperature warning (OTW) level (135C typ), an internal

AGL (Automatic Gain Limiter) will reduce the digital gain automatically. Once the die temperature drops below

the OTW, the device’s digital gain gradually returns to the former setting.

7.4.5 Device State Control

TAS5815 has 5 states with different power dissipation which listed in the Electrical Characteristics Table.

• Shutdown Mode. With PDN pin pull down to GND. All internal LDOs (1.5V for digital core, 5V for analog) are

disabled, all registers are cleared to default value.

Note

Exit from Shutdown Mode and re-enter into Play mode, need to follow up the start-up sequence and

reload all register configurations (which can be generated by PurePath Console3) again.

• Deep Sleep Mode. Register 0x68h [1:0]=00, device stays in Deep Sleep Mode. In this mode, I2C block

and 1.5V LDO for digital core still working, but internal 5V LDO (For AVDD and MOSFET gate driver) is

disabled for low power dissipation. This mode can be used to extend the battery life in some portable speaker

applications. If the host processor stops playing audio for a long time, can be set to Deep Sleep Mode

to minimize power dissipation until host processor starts playing audio again. Unlike the Shutdown Mode

(Pulling PDN Low), entering or exiting Deep Sleep Mode, the DSP keeps active.

• Sleep Mode. Register 0x68h [1:0]=01, device stays in Sleep Mode. In this mode, I2C block, Digital core, DSP

Memory, 5V Analog LDO are stilling working. Unlike the Shutdown Mode (Pull PDN Low), enter or exit Sleep

Mode, DSP is kept active. Exit from this mode and re-enter into play mode, only need to set Register 0x68h

[1:0]=11.

• Output Hi-Z Mode. Register 0x68h [1:0]=10, device stays in Hi-Z Mode. In this mode, only output driver is set

to be Hi-Z state, all other block operate normally. Exit from this mode and re-enter into play mode, only need

to set Register 0x68h [1:0]=11.

• Play Mode. Register 0x68h [1:0]=11, device stays in Play Mode.

7.4.6 Device Modulation

TAS5815 has 3 modulation schemes: BD Modulation, 1SPW modulation and Hybrid modulation. Select

modulation schemes for with Register 0x02 [1:0]-DEVICE_CTRL1.

7.4.6.1 BD Modulation

This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is

driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.

The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the

speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.

The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The

TAS5815

SLOSEA8 – DECEMBER 2024

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