TAS5815PWPR datasheet(86/123 Pages) TI

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8.1.34 CHAN_FAULT Register (Offset = 70h) [Reset = 00h]

CHAN_FAULT is shown in Figure 8-34 and described in Table 8-36.

Return to the Summary Table.

Channel fault

Figure 8-34. CHAN_FAULT Register

RESERVED

CH1DC

CH2DC

CH1OC

CH2OC

R-0h

Table 8-36. CHAN_FAULT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

RESERVED

CH1DC

Channel 1 DC fault. Once there is a DC fault, the fault is latched and

this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT

pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register

(78h) to 1 or this bit keeps 1.

CH2DC

Channel 2 DC fault. Once there is a DC fault, the fault is latched and

this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT

pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register

(78h) to 1 or this bit keeps 1.

CH1OC

Channel 1 over current fault. Once there is a OC fault, the fault is

latched and this bit is set to be 1. Class D output is set to Hi-Z.

Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of

Fault_clear Register (78h) to 1 or this bit keeps 1.

CH2OC

Channel 2 over current fault. Once there is a OC fault, the fault is

latched and this bit is set to be 1. Class D output is set to Hi-Z.

Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of

Fault_clear Register (78h) to 1 or this bit keeps 1.

TAS5815

SLOSEA8 – DECEMBER 2024

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