PI7C8152B datasheet(43/90 Pages) PERICOM

43 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 43 of 90

October 16, 2003 – Revision 1.11

Delayed write request transactions, comprised of I/O write and configuration write

transactions.

Delayed write requests are terminated by target retry on the initiator bus and

are queued in the delayed transaction queue. A delayed write transaction must complete on

the target bus before it completes on the initiator bus.

Delayed write completion transactions, comprised of I/O write and configuration

write transactions.

Delayed write completion transactions complete on the target bus, and the target response

is queued in the buffers. A delayed write completion transaction proceeds

in the direction opposite that of the original delayed write request; that is, a delayed write

completion transaction proceeds from the target bus to the initiator bus.

Delayed read request transactions, comprised of all memory read, I/O read, and

configuration read transactions.

Delayed read requests are terminated by target retry on the initiator bus and are queued in

the delayed transaction queue.

Delayed read completion transactions, comprised of all memory read, I/O read, &

configuration read transactions.

Delayed read completion transactions complete on the target bus, and the read data is

queued in the read data buffers. A delayed read completion transaction proceeds in the

direction opposite that of the original delayed read request; that is, a delayed read

completion transaction proceeds from the target bus to the initiator bus.

PI7C8152x does not combine or merge write transactions:

PI7C8152x does not combine separate write transactions into a single write

transaction—this optimization is best implemented in the originating master.

PI7C8152x does not merge bytes on separate masked write transactions to the same

DWORD address—this optimization is also best implemented in the originating

master.

PI7C8152x does not collapse sequential write transactions to the same address into a

single write transaction—the PCI Local Bus Specification does not permit this

combining of transactions.

5.2

GENERAL ORDERING GUIDELINES

Independent transactions on primary and secondary buses have a relationship only when

those transactions cross PI7C8152x.

The following general ordering guidelines govern transactions crossing PI7C8152x:

The ordering relationship of a transaction with respect to other transactions is

determined when the transaction completes, that is, when a transaction ends with a

termination other than target retry.

Requests terminated with target retry can be accepted and completed in any order with

respect to other transactions that have been terminated with target retry. If the order of

completion of delayed requests is important, the initiator should not start a second

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