PI7C8152B datasheet(59/90 Pages) PERICOM

59 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 59 of 90

October 16, 2003 – Revision 1.11

7.2.2

LOCKED TRANSACTION IN UPSTREAM DIRECTION

PI7C8152x ignores upstream lock and transactions. PI7C8152x will pass these transactions

as normal transactions without lock established.

7.3

ENDING EXCLUSIVE ACCESS

After the lock has been acquired on both initiator and target buses, PI7C8152x must

maintain the lock on the target bus for any subsequent locked transactions until the initiator

relinquishes the lock.

The only time a target-retry causes the lock to be relinquished is on the first transaction of a

locked sequence. On subsequent transactions in the sequence, the target retry has no effect

on the status of the lock signal.

An established target lock is maintained until the initiator relinquishes the lock. PI7C8152x

does not know whether the current transaction is the last one in a sequence of locked

transactions until the initiator de-asserts the LOCK_L signal at end of the transaction.

When the last locked transaction is a delayed transaction, PI7C8152x has already

completed the transaction on the target bus. In this example, as soon as PI7C8152x detects

that the initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state

while FRAME_L is de-asserted, PI7C8152x de-asserts the LOCK_L signal on the target

bus as soon as possible. Because of this behavior, LOCK_L may not be de-asserted until

several cycles after the last locked transaction has been completed on the target bus. As

soon as PI7C8152x has de-asserted LOCK_L to indicate the end of a sequence of locked

transactions, it resumes forwarding unlocked transactions.

When the last locked transaction is a posted write transaction, PI7C8152x de-asserts

LOCK_L on the target bus at the end of the transaction because the lock was relinquished

at the end of the write transaction on the initiator bus.

When PI7C8152x receives a target abort or a master abort in response to a locked delayed

transaction, PI7C8152x returns a target abort or a master abort when the initiator repeats

the locked transaction. The initiator must then de-assert LOCK_L at the end of the

transaction. PI7C8152x sets the appropriate status bits, flagging the abnormal target

termination condition (see Section 3.9). Normal forwarding of unlocked posted and

delayed transactions is resumed.

When PI7C8152x receives a target abort or a master abort in response to a locked posted

write transaction, PI7C8152x cannot pass back that status to the initiator. PI7C8152x

asserts SERR_L on the initiator bus when a target abort or a master abort is received during

a locked posted write transaction, if the SERR_L enable bit is set in the command register.

Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set

in the bridge control register (see Section 6.4).

PI7C8152B Datasheet(PDF) 59 Page - Pericom Semiconductor Corporation

PI7C8152B Datasheet(HTML) 59 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL