LPC2364 datasheet(22/47 Pages) NXP

22 / 47 page

LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

22 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

7.16 SSP serial I/O controller

The LPC2364/66/68 each contain two SSP controllers. The SSP controller is capable of

operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and

slaves on the bus. Only a single master and a single slave can communicate on the bus

during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits

to 16 bits of data ﬂowing from the master to the slave and from the slave to the master. In

practice, often only one of these data ﬂows carries meaningful data.

7.16.1 Features

• Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire

buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.17 SD/MMC card interface (LPC2368 only)

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD

memory cards. The SD card interface conforms to the

SD Multimedia Card Speciﬁcation

Version 2.11.

7.17.1 Features

• The MCI interface provides all functions speciﬁc to the SD/MMC memory card. These

include the clock generation unit, power management control, and command and data

transfer.

• Conforms to Multimedia Card Speciﬁcation v2.11.

• Conforms to Secure Digital Memory Card Physical Layer Speciﬁcation, v0.96.

• Can be used as a multimedia card bus or a secure digital memory card bus host. The

SD/MMC can be connected to several multimedia cards or a single secure digital

memory card.

• DMA supported through the GPDMA controller.

7.18 I2C-bus serial I/O controllers

The LPC2364/66/68 each contain three I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus, it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2364/66/68 supports bit rates up to 400 kbit/s (Fast

I2C-bus).

LPC2364 Datasheet(PDF) 22 Page - NXP Semiconductors

LPC2364 Datasheet(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL