LPC2364 datasheet(16/47 Pages) NXP

16 / 47 page

LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

16 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs

the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ

latency is achieved when only one request is classiﬁed as FIQ, because then the FIQ

service routine can simply start dealing with that device. But if more than one request is

assigned to the FIQ class, the FIQ service routine can read a word from the VIC that

identiﬁes which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs, which include all interrupt requests that are not classiﬁed as FIQs, have a

programmable interrupt priority. When more than one interrupt is assigned the same

priority and occur simultaneously, the one connected to the lowest numbered VIC channel

will be serviced ﬁrst.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the

ARM processor. The IRQ service routine can start by reading a register from the VIC and

jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several

interrupt ﬂags. Individual interrupt ﬂags may also represent more than one interrupt

source.

Any pin on PORT0 and PORT2 (total of 42 pins) regardless of the selected function, can

be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such

interrupt request coming from PORT0 and/or PORT2 will be combined with the EINT3

interrupt requests.

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undeﬁned.

7.7 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2364/66/68

peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receive. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the AHB master.

7.7.1 Features

• Two DMA channels. Each channel can support a unidirectional transfer.

• The GPDMA can transfer data between the 8 kB SRAM and peripherals such as the

SD/MMC, two SSP, and I2S interfaces.

LPC2364 Datasheet(PDF) 16 Page - NXP Semiconductors

LPC2364 Datasheet(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Datasheet Download

Link URL