LPC2364 datasheet(37/47 Pages) NXP

37 / 47 page

LPC2364_66_68_2

Preliminary data sheet

Rev. 02 — 1 October 2007

37 of 47

NXP Semiconductors

LPC2364/66/68

Fast communication chip

[1]

Conditions: VSSA =0V, VDDA = 3.3 V.

[2]

The ADC is monotonic, there are no missing codes.

[3]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.

[4]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5]

The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 4.

[6]

The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 4.

[7]

The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC

and the ideal transfer curve. See Figure 4.

[8]

See Figure 5.

gain error

[1][6] --

±0.5

absolute error

[1][7] --

±4

LSB

Rvsi

voltage source interface

resistance

[8] --40

Ω

Table 6.

ADC static characteristics …continued

VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise speciﬁed; ADC frequency 4.5 MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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