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TMP93CS32F Datasheet(PDF) 51 Page - Toshiba Semiconductor |
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TMP93CS32F Datasheet(HTML) 51 Page - Toshiba Semiconductor |
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51 / 180 page  TMP93CS32 2004-02-10 93CS32-49 3.5.4 Port 3 (P30 to P32, P35) Port 3 is an 4-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting resets all bits of output latch P3, control register P3CR (bits 0 and 1 are unused), and function register P3FC to 0. Resetting also outputs 1 from P30 and P31. In addition to functioning as a general-purpose I/O port, Port 3 also shares functions as an I/O for the CPU’s control/status signal. With the TMP93CS32, when P30 pin is defined as RD signal output mode (<P30F> = 1), clearing the output latch register <P30> to 0 outputs the RD strobe (used for the pseudo static RAM) from the P30 pin even when the internal address area is accessed. If the output latch register <P30> remains 1, the RD strobe signal is output only when the external address area is accessed. (1) P30 ( RD ) and P31 ( WR ) Figure 3.5.6 Port 3 (P30 and P31) Function control (on bit basis) Reset P3FC write S Output latch P3 write P3 read Output buffer P30 ( RD ) P31 ( WR ) S A Selector B RD , WR |
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