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AD9084-DF Datasheet(PDF) 48 Page - Analog Devices |
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AD9084-DF Datasheet(HTML) 48 Page - Analog Devices |
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48 / 50 page ![]() Data Sheet AD9084 THEORY OF OPERATION analog.com Rev. 0 | 48 of 50 ► Course numerically controlled oscillator (CNCO) and fine numeri- cally controlled oscillator (FNCO) fast frequency hopping ► CFIR and PFILT profiles hopping ► CDDC and CDUC 1× to 8× reconfigured on the fly ► CDDC, CDUC, FDDC, and FDUC reconfigured between multiple decimation and interpolation ratios on the fly ► Interface ► SPI: maximum SCLK rate 50MHz ► HSCI: maximum rate 1.6Gbps in DDR mode ► JESD204B and JESD204C: 16Gbps and 28.21Gbps ► 24 lanes for receive, and 24 lanes for transmit ► Receive AGC support ► Fast detect with low latency for fast AGC control ► Signal monitor for slow AGC control ► Power amplifier downstream protection circuitry ► Additional digital features are listed in the UG-2300 Device User Guide. |
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