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MSC8144EC Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc |
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MSC8144EC Datasheet(HTML) 68 Page - Freescale Semiconductor, Inc |
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68 / 80 page ![]() MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6 Hardware Design Considerations Freescale Semiconductor 68 3.4.1.3 ECC Unused Pin Connections When the error code corrected mechanism is not used in any 32- or 16-bit DDR configuration, refer to Table 59 to determine the correct pin connections. 3.4.2 Serial RapidIO Interface Related Pins 3.4.2.1 Serial RapidIO interface Is Not Used 3.4.2.2 Serial RapidIO Specific Lane Is Not Used Table 58. Connectivity of Unused ECC Mechanism Pins Signal Name Pin connection MECC[0–7] pull-up to VDDDDR ECC_MDM NC ECC_MDQS pull-down to GND ECC_MDQS pull-up to VDDDDR Table 59. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used Signal Name Pin Connection SRIO_IMP_CAL_RX GND SRIO_IMP_CAL_TX GND SRIO_REF_CLK GND SRIO_REF_CLK GND SRIO_RXD[0–3] GND SRIO_RXD[0–3] GND SRIO_TXD[0–3] NC SRIO_TXD[0–3] NC VDDRIOPLL GND GNDRIOPLL GND GNDSXP GND GNDSXC GND VDDSXP GND VDDSXC GND Table 60. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used Signal Name Pin Connection SRIO_IMP_CAL_RX in use SRIO_IMP_CAL_TX in use SRIO_REF_CLK in use SRIO_REF_CLK in use SRIO_RXDx GNDSXC SRIO_RXDx GNDSXC |
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