START

MSB

DEVICE ADDRESS

R/W

LSB

ACK

SCL

SDA

REGISTER ADDRESS

REGISTER DATA

ACK

ACK

STOP

IN-

IN+

LM48560

SINGLE-ENDED

INPUT

LM48560

SNAS513F – AUGUST 2011 – REVISED NOVEMBER 2015

www.ti.com

8.4.2 Single-Ended Input Configuration

The LM48560 device is compatible with single-ended sources. When configured for single-ended inputs, input

capacitors must be used to block and DC component at the input of the device. Figure 25 shows the typical

single-ended applications circuit.

Figure 25. Single-Ended Input Configuration

8.5 Programming

8.5.1 Read/Write I2C Compatible Interface

The LM48560 device is controlled through an I2C compatible serial interface that consists of a serial data line

(SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The

LM48560 device and the master can communicate at clock rates up to 400 kHz. Figure 1 shows the I2C interface

timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48560 device is a

transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission

sequence is framed by a START condition and a STOP condition Figure 2. Each data word, device address and

data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse Figure 26. The

LM48560 device address is 1101111.

8.5.2 Write Sequence

The example write sequence is shown in Figure 26. The START signal, the transition of SDA from HIGH to LOW

while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.

The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0

indicating the master is writing to the LM48560 device). The data is latched in on the rising edge of the clock.

Each address bit must be stable while SDA is HIGH. After the R/W bit is transmitted, the master device releases

SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48560 device

receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK).

Once the master device registers the ACK bit, the 8-bit register address word is sent, MSB first. Each data bit

should be stable while SCL is HIGH. After the 8-bit register address is sent, the LM48560 device sends another

ACK bit. Upon receipt of the acknowledge, the 8-bit register data is sent, MSB first. The register data word is

followed by an ACK, upon receipt of which, the master issues a STOP bit, allowing SDA to go high while SDA is

high.

Figure 26. Example I2C Write Cycle

8.5.3 Read Sequence

The example read sequence is shown in Figure 27. The START signal, the transition of SDA from HIGH to LOW

while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.

14

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